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| MT93L04 128-Channel Voice Echo Canceller Data Sheet Features * MT93L04 is a Multi-chip Module (MCM) consisting of 4 MT93L00 devices thus providing 128 channels of 64 msec Echo Cancellation Each device (MT93L00) is independent of the each other Each device has the capability of cancelling echo over 32 channels The MCM module provides more than 40% board space savings Each device (MT93L00) can be programmed independently in any mode e.g back to back or extended delay to provide capability of cancelling different echo tails Each device has the same Jtag identification code Ordering Information MT93L04AG 365 Ball BGA Trays MT93L04AG2 365 Ball BGA** Trays **Pb Free Tin/Silver/Copper -40C to +85C * * Echo Canceller pools DCME, satellite and multiplexer systems January 2006 * * * * Description The MT93L04 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The MT93L04 architecture contains 64 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 128 channels of 64 milliseconds to 64 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The MT93L04 supports ITU-T G.165 and G.164 tone disable requirements. * Applications * * * * Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation Wireless base stations MT93L00 MT93L00 1 4 MT93L00 MT93L00 2 3 Figure 1 - MT93L04 is MULTI-CHIP Module Consisting of 4 MT93L00 Devices 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2006, Zarlink Semiconductor Inc. All Rights Reserved. MT93L04 Data Sheet VDD1 (3.3V) VSS VDD2 (1.8V) ODE Echo Canceller Pool Rin Sin MCLK Fsel PLL Serial to Parallel Group 0 ECA/ECB Group 1 ECA/ECB Group 2 ECA/ECB Group 3 ECA/ECB Parallel to Serial Rout Sout Group 4 ECA/ECB Group 5 ECA/ECB Group 6 ECA/ECB Group 7 ECA/ECB Group 8 ECA/ECB Group 9 ECA/ECB Group 10 ECA/ECB Group 11 ECA/ECB Group 12 ECA/ECB C4i F0i Timing Unit Group 13 ECA/ECB Group 14 ECA/ECB Group 15 ECA/ECB Note: Refer to Figure 4 for Echo Canceller block diagram IC0 RESET Microprocessor Interface Test Port DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST Figure 2 - Functional Block Diagram for Single MT93L00 (32 channels) Features of Single MT93L00 * * * * * * * * * * * * * * * * * * Independent multiple channels of echo cancellation; from 32 channels of 64 ms to 16 channels of 128 ms with the ability to mix channels at 128 ms or 64 ms in any combination Independent Power Down mode for each group of 2 channels for power management ITU-T G.165 and G.168 compliant Field proven, high quality performance Compatible to ST-BUS and GCI interface at 2 Mb/s serial PCM PCM coding, /A-Law ITU-T G.711 or sign magnitude Per channel Fax/Modem G.164 2100 Hz or G.165 2100 Hz phase reversal Tone Disable Per channel echo canceller parameters control Transparent data transfer and mute Fast reconvergence on echo path changes Non-Linear Processor with high quality subjective performance Protection against narrow band signal divergence Offset nulling of all PCM channels 10 MHz or 20 MHz master clock operation 3.3 V pads and 1.8 V Logic core operation with 5-Volt tolerant inputs No external memory required Non-multiplexed microprocessor interface IEEE-1149.1 (JTAG) Test Access Port 2 Zarlink Semiconductor Inc. MT93L04 Data Sheet 1 1 A B C D E F G H Tsig(12)_d1 2 3 SC_in_d1 4 5 FOIB_d1 6 7 Tsig(7)_d1 8 9 Tsig(1)_d1 10 11 Fsel_d4 12 13 Tsig(14)_d4 14 15 SC_in_d4 16 17 SC_set_d4 18 19 Sout_d4 20 A Rout_d1 ODE_d1 Sin_d1 Sout_d1 C4IB A(2)_d1 Rin_d1 D(7)_d1 SG1(d1) A(1)_d1 D(6)_d1 D(5)_d1 A(3)_d1 A(5)_d1 A(4)_d1 A(7)_d1 A_IC1_d1 A(6)_d1 Tsig(6)_d1 Tsig(3)_d1 Tsig(5)_d1 Tsig(4)_d1 A(8)_d1 A(9)_d1 A_IC2_d1 Tsig(0)_d1 Tsig(2)_d1 A(10)_d1 SG1_d4 Tsig(10)_d4 DT1_d4 Tsig(11)_d4 SC_fclk_d4 TM2_d4 SM_mclk_d4 Sin_d4 FOIB_d4 C4IB SC_en_d4 Mclk_d4 Tsig(9)_d4 Tsig(13)_d4 Halt_d4 Step_d4 AT1_d4 PLLVSS1_d4 TMS_d4 Tsig(5)_d4 Rout_d4 PLLVDD_d4 TDI_d4 Tsig(4)_d4 A(10)_d4 A_IC2_d4 A(7)_d4 A(6)_d4 A(4)_d4 A(5)_d4 A(1)_d4 A(3)_d4 A(9)_d4 TD0_d4 Rin_d4 Tsig(6)_d4 ODE_d4 Tsig(2)_d4 Tsig(7)_d4 SC_set_d1 ST_mclk_d4 SC_Fclk_d1 Tsig(15)_d1 SM_mclk_d1 SC_reset_d1 B C D E F G H Tsig(11)_d1 TM2_d1 Tsig(13)_d1 Fsel_d1 Tm1_d1 Halt_d1 ST_mclk_d1 SC_en_d1 SC_reset_d4 Tsig(9)_d1 Tsig(8)_d4 Tsig(12)_d4 Tsig(3)_d4 Tsig(1)_d4 Tsig(0)_d4 A_IC1_d4 Tsig(8)_d1 Tsig(10)_d1 A(0)_d1 Tm1_d4 PLLVSS2_d4 Tsig(14)_d1 Mclk_d1 Trstb_d4 Tsig(15)_d4 PLLVDD_d1 Step_d1 AT1_d1 DT1_d1 RESETB_d4 Vdd1 D(4)_d1 Vdd1 Vdd2 Vdd2 Vdd2 Vdd2 Vdd1 Vdd1 TCK_d4 IRQB_d4 Test_en_d4 A(8)_d4 PLLVSS1_d1 PLLVSS2_d1 D(3)_d1 R/WB_d1 D(0)_d1 TDI_d1 TD0_d1 TMS_d1 CSB_d1 DTAB_d1 Test_En_d1 Dsb_d1 D(2)_d1 Vdd1 Vss Vss Vss Vss Vss Vss Vdd1 Dsb_d4 R/WB_d4 A(0)_d4 D(7)_d4 D(1)_d4 D(6)_d4 DTAB_d4 Csb_d4 D(0)_d4 C4IB_d3 SM_mclk_d3 A(2)_d4 D(5)_d4 J K L M N P R T TCK_D1 IRQB_d1 Vdd2 Vdd2 Vss Vss Vss Vss Vss Vss Vdd2 J D(4)_d4 D(2)_d4 D(3)_d4 Rin_d3 FOIB_d3 Sout_d3 Tsig(7)_d3 Tsig(6)_d3 SC_set_d3 ST_mclk_d3 Tsig(4)_d3 Tsig(1)_d3 A_IC2_d3 A(10)_d3 SC_reset_d3 A(8)_d3 A(7)_d3 A(4)_d3 A(5)_d3 A(6)_d3 A(1)_d3 D(7)_d3 D(0)_d3 D(3)_d3 DSB_d3 IRQB_d3 DTAB_d3 D(1)_d3 D(4)_d3 D(5)_d3 A(2)_d3 A(3)_d3 A(9)_d3 A_ICI_d3 Tsig(0)_d3 Tsig(2)_d3 Tsig(3)_d3 Rout_d3 TRSTB_D1 D(1)_d1 Vss Vss Vss Vss Vss Vss Vdd2 RESETB_d1 Sout_d2 Sin_d2 SC_in_d2 C4IB_d2 K L M SC_en_d2 Vdd2 Vss Vss Vss Vss Vss Vss Vdd2 SM_mclk_d2 SC_Fclk_d2 ST_mclk_d2 Vdd2 Vss Vss Vss Vss Vss Vss Vdd2 Sin_d3 Tsig(5)_d3 SC_reset_d2 SC_set_d2 FOIB_d2 Tsig(9)_d2 Rin_d2 Tsig(8)_d2 Ode_d2 Rout_d2 ODE_d3 Vdd1 Vss Vss Vss Vss Vss Vss Vdd1 N P R T U V W Y Tsig(13)_d2 Tsig(6)_d2 Vdd1 Vdd1 Vdd1 Vdd1 SC_en_d3 SC_in_d3 Tsig(10)_d2 Tsig(11)_d2 TM2_d2 Tsig(7)_d2 Tsig(4)_d2 SG1_d2 Tsig(3)_d2 Tsig(5)_d2 Tsig(1)_d2 Irqb_d2 DTAB_d2 Test_en_d2 Tms_d2 D(2)_d2 D(7)_d2 D(3)_d2 D(0)_d2 Csb_d2 RESETB_d2 D(1)_d2 D(4)_d2 D(5)_d2 D(6)_d2 A(3)_d2 A(10)_d2 A(2)_d2 A(8)_d2 A_IC2_d2 A_IC1_d2 Tsig(0)_d2 A(9)_d2 A(1)_d2 A(7)_d2 A(0)_d2 A(4)_d2 DT1_d3 A(6)_d2 A(5)_d2 Mclk_d3 AT1_d3 Step_d3 Fsel_d3 Tsig(15)_d3 Vdd2 Vdd2 Vdd2 Vdd2 Vdd1 Tsig(12)_d2 Tsig(14)_d2 TM1_d2 Tsig(15)_d2 Halt_d2 Tsig(11)_d3 SC_fclk_d3 Tsig(13)_d3 Tm2_d3 Tsig(10)_d3 Tsig(8)_d3 U DT1_d2 PLLVSS2_d2 Tsig(12)_d3 Tsig(9)_d3 R/WB_d3 Test_en_d3 D(2)_d3 RESETB_d3 TCK_d3 CSB_d3 Trstb_d3 TDO_d3 Mclk_d2 AT1_d2 Step_d2 Fsel_d2 TD0_d2 PLLVDD_d2 PLLVSS1_d2 Tsig(2)_d2 Tsig(14)_d3 TDI_d3 A(0)_d3 D(6)_d3 V W Y 1 R/WB_d2 DSB_d2 PLLVSS2_d3 SG1_d3 TMS_d3 Trstb_d2 PLLVDD_d3 TM1_d3 PLLVSS1_d3 Halt_d3 Tck_d2 TDI_d2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - A1 corner is identified by metallized markings. Figure 3 - 365 Ball BGA 3 Zarlink Semiconductor Inc. MT93L04 Pin Description Signal Name VDD1 = 3.3V VDD2 = 1.8V Signal Type Power Power BGA Ball # Signal Description Data Sheet R6, R8, R13, R15, N15,H15, Positive Power Supply. Nominally 3.3 volt. F15,F13,F8,F6,H6,N6, P6, VDD1 = I/O Voltage R9,R10,R11,R12,M15, L15,K15,J15,F12,F11, F10,F9,J6, K6, L6,M6, Positive Power Supply. Nominally 1.8 volt. VDD2 = Core Voltage VSS Power H8,H9,H10,H11,H12, H13, Ground J8, J9,J10,J11, J12,J13,K8,K9,K10,K11,K1 2,K13 L8,L9,L10, L11,L12,L13,M8,M9,M10,M 11,M12, M13, N8, N9,N10,N11,N12,N13 J4 Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. Internal Connection. Connected to VSS for normal operation Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. DEVICE 1 TMS_d1 User Signal TDI_d1 User Signal J3 TDO_d1 User Signal J2 TCK_d1 TRSTB_d1 User Signal User Signal J1 K1 Test_En_d1 RESETB_d1 ICO User Signal H1 K2 4 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name IRQB_d1 Signal Type User Signal BGA Ball # J5 Signal Description Data Sheet Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. DSB_d1 User Signal H2 CSB_d1 User Signal K3 R/WB_d1 User Signal H3 DTAB_d1 User Signal K4 D(0)_d1 D(1)_d1 D(2)_d1 D(3)_d1 D(4)_d1 D(5)_d1 D(6)_d1 D(7)_d1 A(0)_d1 A(1)_d1 A(2)_d1 A(3)_d1 A(4)_d1 A(5)_d1 A(6)_d1 A(7)_d1 A(8)_d1 A(9)_d1 A(10)_d1 User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal H4 K5 H5 G4 G5 F4 F5 E5 D4 E6 D5 E7 D7 E8 E10 D8 D10 C10 B10 Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. 5 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name A_IC1_d1 A_IC2_d1 Tsig(0)_d1 Tsig(1)_d1 Tsig(2)_d1 Tsig(3)_d1 Tsig(4)_d1 Tsig(5)_d1 Tsig(6)_d1 Tsig(7)_d1 ODE_d1 Signal Type ICO ICO NC NC NC NC NC NC NC NC User Signal BGA Ball # E9 A8 A10 A9 B9 C9 D9 C8 B8 A7 B7 Signal Description Data Sheet Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Output Drive Enable (Input). This input pin is logically AND'd with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Sout_d1 User Signal C7 Rout_d1 User Signal A6 Sin_d1 User Signal B6 Rin_d1 User Signal D6 6 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name FOIb_d1 Signal Type User Signal BGA Ball # A5 Signal Description Data Sheet Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. The pin must be left open for normal operation. Internal Connection. The pin must be left open for normal operation. Internal Connection. The pin must be left open for normal operation. Internal Connection. The pin must be left open for normal operation. Internal Connection. The pin must be left open for normal operation. Internal Connection. The pin must be left open for normal operation. Internal Connection. The pin must be left open for normal operation. Internal Connection. The pin must be left open for normal operation. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation C4IB_d1 User Signal C6 SC_set_d1 SM_mclk_d1 ST_mclk_d1 SC_en_d1 SC_In_d1 SC_Reset:_d1 SC_Fclk_d1 Tsig(8)_d1 Tsig(9)_d1 Tsig(10)_d1 Tsig(11)_d1 Tsig(12)_d1 Tsig(13)_d1 Tsig(14)_d1 Tsig(15)_d1 Tm1_d1 Tm2_d1 ICO ICO ICO ICO ICO ICO ICO NC NC NC NC NC NC NC NC ICO ICO B5 A4 B4 C5 A3 B3 A2 C4 C3 D3 B2 A1 C2 E3 B1 D2 C1 7 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name Sg1_d1 DT1_d1 MCLK_d1 Signal Type ICO NC User Signal BGA Ball # E4 F3 E2 Signal Description Data Sheet Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation PLL Ground. Must be connected to VSS PLL Power Supply. Must be connected to VDD2 PLL Ground. Must be connected to VSS No connection. The pin must be left open for normal operation. Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. Fsel_d1 User Signal D1 Halt_d1 Step_d1 PLLVSS1_d1 PLLVDD_d1 PLLVSS2_d1 AT1_d1 DEVICE 2 TMS_d2 ICO ICO Power Power Power NC E1 F2 G3 F1 G2 G1 Signal V4 TDI_d2 Signal Y2 TDO_d2 Signal W3 TCK_d2 TRSTB_d2 Signal Signal Y3 W4 8 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name Test_En_d2 RESETB_d2 Signal Type ICO Signal BGA Ball # V5 Y4 Signal Description Data Sheet Internal Connection. Connected to VSS for normal operation Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. IRQB_d2 Signal U5 DSB_d2 Signal W5 CSB_d2 Signal Y5 R/WB_d2 Signal V6 DTAB_d2 Signal U6 D(0)_d2 D(1)_d2 D(2)_d2 D(3)_d2 D(4)_d2 D(5)_d2 D(6)_d2 D(7)_d2 Signal Signal Signal Signal Signal Signal Signal Signal W6 Y6 V7 W7 Y7 Y8 W8 V8 Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. 9 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name A(0)_d2 A(1)_d2 A(2)_d2 A(3)_d2 A(4)_d2 A(5)_d2 A(6)_d2 A(7)_d2 A(8)_d2 A(9)_d2 A(10)_d2 A_IC1_d2 A_IC2_d2 Tsig(0)_d2 Tsig(1)_d2 Tsig(2)_d2 Tsig(3)_d2 Tsig(4)_d2 Tsig(5)_d2 Tsig(6)_d2 Tsig(7)_d2 ODE_d2 Signal Type Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal ICO ICO NC NC NC NC NC NC NC NC Signal BGA Ball # U9 V9 W9 Y9 U10 T10 T9 V10 W10 U8 Y10 T8 T7 U7 T6 U4 T5 R5 T4 P5 P4 N5 Signal Description Data Sheet Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Output Drive Enable (Input). This input pin is logically AND'd with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. 10 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name Sout_d2 Signal Type Signal BGA Ball # L1 Signal Description Data Sheet Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Rout_d2 Signal N4 Sin_d2 Signal L2 Rin_d2 Signal N3 FOIb_d2 Signal N2 C4IB_d2 Signal L3 SC_set_d2 SM_mclk_d2 ST_mclk_d2 SC_en_d2 SC_In_d2 SC_Reset:_d2 SC_Fclk_d2 Tsig(8)_d2 Tsig(9)_d2 Tsig(10)_d2 ICO ICO ICO ICO ICO ICO ICO NC NC NC N1 L4 M5 L5 M1 M2 M3 M4 P1 P2 11 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name Tsig(11)_d2 Tsig(12)_d2 Tsig(13)_d2 Tsig(14)_d2 Tsig(15)_d2 Tm1_d2 Tm2_d2 Sg1_d2 DT1_d2 MCLK_d2 Signal Type NC NC NC NC NC ICO ICO ICO NC Signal BGA Ball # R1 R2 P3 T1 U1 T2 R3 R4 V1 U2 Signal Description Data Sheet No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation PLL Ground. Must be connected to VSS PLL Power Supply. Must be connected to VDD2 PLL Ground. Must be connected to VSS No connection. The pin must be left open for normal operation. Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. Fsel_d2 Signal W1 Halt_d2 Step_d2 PLLVSS1_d2 PLLVDD_d2 PLLVSS2_d2 AT1_d2 DEVICE 3 TMS_d3 ICO ICO Power Power Power NC T3 V2 Y1 W2 U3 V3 Signal W13 12 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name TDI_d3 Signal Type Signal BGA Ball # V13 Signal Description Data Sheet Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. Internal Connection. Connected to VSS for normal operation Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. TDO_d3 Signal Y14 TCK_d3 TRSTB_d3 Signal Signal W14 Y15 Test_En_d3 RESETB_d3 ICO Signal V14 W15 IRQB_d3 Signal Y16 DSB_d3 Signal Y17 CSB_d3 Signal W16 R/WB_d3 Signal V15 B_d3 Signal Y18 13 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name D(0)_d3 D(1) _d3 D(2)_d3 D(3)_d3 D(4)_d3 D(5)_d3 D(6)_d3 D(7)_d3 A(0)_d3 A(1)_d3 A(2)_d3 A(3)_d3 A(4)_d3 A(5)_d3 A(6)_d3 A(7)_d3 A(8)_d3 A(9)_d3 A(10)_d3 A_IC1_d3 A_IC2_d3 Tsig(0)_d3 Tsig(1)_d3 Tsig(2)_d3 Tsig(3)_d3 Tsig(4)_d3 Tsig(5)_d3 Tsig(6)_d3 Signal Type Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal ICO ICO NC NC NC NC NC NC NC BGA Ball # W17 Y19 V16 W18 Y20 W19 V17 V18 U18 V19 W20 V20 T18 U19 U20 T19 R18 T20 R17 R19 P18 R20 P19 P20 N19 N18 M17 M18 Signal Description Data Sheet Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. 14 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name Tsig(7)_d3 ODE_d3 Signal Type NC Signal BGA Ball # M19 M20 Signal Description Data Sheet No connection. The pin must be left open for normal operation. Output Drive Enable (Input). This input pin is logically AND'd with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Sout_d3 Signal L20 Rout_d3 Signal N20 Sin_d3 Signal M16 Rin_d3 Signal L19 FOIb_d3 Signal L18 C4IB_d3 Signal L17 SC_set_d3 SM_mclk_d3 ST_mclk_d3 SC_en_d3 SC_In_d3 SC_Reset:_d3 ICO ICO ICO ICO ICO ICO N17 L16 N16 P17 P16 R16 15 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name SC_Fclk_d3 Tsig(8)_d3 Tsig(9)_d3 Tsig(10)_d3 Tsig(11)_d3 Tsig(12)_d3 Tsig(13)_d3 Tsig(14)_d3 Tsig(15)_d3 Tm1_d3 Tm2_d3 Sg1_d3 DT1_d3 MCLK_d3 Signal Type ICO NC NC NC NC NC NC NC NC ICO ICO ICO NC Signal BGA Ball # T17 U17 U16 T16 T15 U15 T14 U14 T13 Y11 U13 W11 V11 U11 Signal Description Data Sheet Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation PLL Ground. Must be connected to VSS PLL Power Supply. Must be connected to VDD2 Fsel_d3 Signal T12 Halt_d3 Step_d3 PLLVSS1_d3 PLLVDD_d3 ICO ICO Power Power Y13 T11 Y12 W12 16 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name PLLVSS2_d3 AT1_d3 DEVICE 4 TMS_d4 Signal E16 Signal Type Power NC V12 U12 BGA Ball # Signal Description Data Sheet PLL Ground. Must be connected to VSS No connection. The pin must be left open for normal operation. Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. Internal Connection. Connected to VSS for normal operation Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. TDI_d4 Signal D17 TDO_d4 Signal C18 TCK_d4 TRSTB_d4 Signal Signal F16 E17 Test_En_d4 RESETB_d4 ICO Signal G16 F17 IRQB_d4 Signal G17 DSB_d4 Signal H16 17 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name CSB_d4 Signal Type Signal K16 BGA Ball # Signal Description Data Sheet Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. R/WB_d4 Signal H17 DTAB_d4 Signal K17 D(0)_d4 D(1)_d4 D(2)_d4 D(3)_d4 D(4)_d4 D(5)_d4 D(6)_d4 D(7)_d4 A(0)_d4 A(1)_d4 A(2)_d4 A(3)_d4 A(4)_d4 A(5)_d4 A(6)_d4 A(7)_d4 A(8)_d4 A(9)_d4 A(10)_d4 A_IC1_d4 A_IC2_d4 Tsig(0)_d4 Tsig(1)_d4 Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal ICO ICO NC NC K18 J16 K19 K20 J20 J19 J18 J17 H18 H19 H20 G20 G19 G18 F20 F19 F18 E20 E19 D20 E18 D19 C20 Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. 18 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name Tsig(2)_d4 Tsig(3)_d4 Tsig(4)_d4 Tsig(5)_d4 Tsig(6)_d4 Tsig(7)_d4 ODE_d4 Signal Type NC NC NC NC NC NC Signal B20 C19 D18 C17 B19 A20 B18 BGA Ball # Signal Description Data Sheet No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Output Drive Enable (Input). This input pin is logically AND'd with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). Internal Connection. Connected to VSS for normal operation Sout_d4 Signal A19 Rout_d4 Signal C16 Sin_d4 Signal B17 Rin_d4 Signal A18 FOIb_d4 Signal B16 C4IB_d4 Signal C15 SC_set_d4 ICO A17 19 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name SM_mclk_d4 ST_mclk_d4 SC_en_d4 SC_In_d4 SC_Reset:_d4 SC_Fclk_d4 Tsig(8)_d4 Tsig(9)_d4 Tsig(10)_d4 Tsig(11)_d4 Tsig(12)_d4 Tsig(13)_d4 Tsig(14)_d4 Tsig(15)_d4 Tm1_d4 Tm2_d4 Sg1_d4 DT1_d4 MCLK_d4 Signal Type ICO ICO ICO ICO ICO ICO NC NC NC NC NC NC NC NC ICO ICO ICO NC Signal A16 B15 C14 A15 B14 A14 C13 D12 A12 B12 C12 E11 A13 E12 D11 B13 C11 B11 D13 BGA Ball # Signal Description Data Sheet Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. 20 Zarlink Semiconductor Inc. MT93L04 Pin Description (continued) Signal Name Fsel_d4 Signal Type Signal A11 BGA Ball # Signal Description Data Sheet Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation PLL Ground. Must be connected to VSS PLL Power Supply. Must be connected to VDD2 PLL Ground. Must be connected to VSS No connection. The pin must be left open for normal operation. Halt_d4 Step_d4 PLLVSS1_d4 PLLVDD_d4 PLLVSS2_d4 AT1_d4 ICO ICO Power Power Power NC E13 D14 E14 D15 D16 E15 21 Zarlink Semiconductor Inc. MT93L04 Description of the Single MT93L00 Device Overview Data Sheet The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, providing full-duplex 64 ms echo cancellation. Each echo canceller contains the following main elements (see Figure 4). * * * * * * * * * * * * Adaptive Filter for estimating the echo channel Subtractor for cancelling the echo Double-Talk detector for disabling the filter adaptation during periods of double-talk Path Change detector for fast reconvergence on major echo path changes Instability Detector to combat oscillation in very low ERL environments Non-Linear Processor for suppression of residual echo Disable Tone Detectors for detecting valid disable tones at send and receive path inputs Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals Offset Null filters for removing the DC component in PCM channels 12 dB attenuator for signal attenuation Parallel controller interface compatible with Motorola microcontrollers PCM encoder/decoder compatible with /A-Law ITU-T G.711 or Sign-Magnitude coding Each echo canceller in the MT93L00 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. 22 Zarlink Semiconductor Inc. MT93L04 Data Sheet Sin (channel N) m/A-Law/ Linear Offset Null + - Non-Linear Processor Linear/ m/A-Law MuteS Microprocessor Interface Sout (channel N) Adaptive Filter Control Disable Tone Detector ST-BUS PORT2 Programmable Bypass Instability Detector Linear/ m/A-Law Double-Talk Detector Path Change Detector Disable Tone Detector ST-BUS PORT1 Narrow-Band Detector MuteR Rout (channel N) 12dB Attenuator Offset Null m/A-Law/ Linear Rin (channel N) Echo Canceller (N), where 0 N 31 Figure 4 - Echo Canceller Functional Block Diagram Adaptive Filter The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is divided into two sections. Each section contains 512 taps providing 64 ms of echo estimation. In Normal configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to Back configuration, the first section is used in the receive direction and the second section is used in the transmit direction for the same channel. Double-Talk Detector Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition: Lsin > Lrin + 20log10(DTDT) where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0. A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo return. During these periods, the adaptation process is slowed down but it is not halted. 23 Zarlink Semiconductor Inc. MT93L04 Data Sheet In G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to get additional guardband, the DTDT is set internally to 0.5625 (-5 dB). In some applications the return loss can be higher or lower than 6 dB. The MT93L00 allows the user to change the detection threshold to suit each application's need. This threshold can be set by writing the desired threshold value into the DTDT register. The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: DTDT(hex) = hex(DTDT(dec) * 32768) where 0 < DTDT(dec) < 1 Example: For DTDT = 0.5625 (-5dB), the hexadecimal value becomes hex(0.5625 * 32768) = 4800h Path Change Detector Integrated into the MT93L00A is a Path Change Detector. This permits fast reconvergence when a major change occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is achieved, but at a much slower speed. The Path Change Detector is activated by setting the PathDet bit in Control Register A3/B3 to "1". An optional path clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection of a major path change. Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible. The MT93L00 uses an NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated by the following equation: TSUP = Lrin + 20log10(NLPTHR) where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed in dBm0. When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal by an additional 36 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP. The NLP processor can be disabled by setting the NLPDis bit to "1" in Control Register 2. 24 Zarlink Semiconductor Inc. MT93L04 Data Sheet The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: NLPTHR(hex) = hex(NLPTHR(dec) * 32768) where 0 < NLPTHR(dec) < 1 The comfort noise injector can be disabled by setting the INJDis bit to "1" in Control Register A1/B1. It should be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled. If the comfort noise injector is unable to correctly match the level of the background noise (because of peculiar spectral characteristics, for example), the injected level can be fine-tuned using the Noise Scaling register. A neutral value of 80(hex) will prevent any scaling. Values less than 80(hex) will reduce the noise level, values greater than 80(hex) will increase the noise level. The scaling is done linearly. Example: To decrease the comfort noise level by 3 dB, the register value would be 10 ^ (-3 / 20) * 128 = 0.71 * 128 = 91(dec) = 5B(hex) The default factory setting for the Noise Scaling register should be adequate for most operating environments. It is unlikely that it will need to be changed. It has also been set to a value which will ensure G.168 compliance. Disable Tone Detector G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (21 Hz) sine wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees ( 25 degrees) every 450 ms ( 25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone Detector will trigger. G.164 recommendation defines the disable tone as a 2100 Hz (21 Hz) sine wave with a power level between 0 to -31 dBm0. If the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal, the Tone Detector will trigger. The MT93L00 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 5 and to the Interrupts section. Rin Sin Tone Detector Tone Detector Echo Canceller A ECA Status reg TD bit Rin Sin Tone Detector Tone Detector Echo Canceller B ECB Status reg TD bit Figure 5 - Disable Tone Detection Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the 25 Zarlink Semiconductor Inc. MT93L04 Data Sheet frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is generated (i.e., IRQ pin low). The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per channel basis. When the PHDis bit is set to 1, G.164 tone disable requirements are selected. In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state. Instability Detector In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability problems in the adaptive filter. This instability can result in variable pitched ringing or oscillation. Should this ringing occur, the Instability Detector will activate and suppress the oscillations. The Instability Detector is activated by setting the RingClr bit in Control Register A3/B3 to "1". Narrow Band Signal Detector (NBSD) Single or dual frequency tones (i.e., DTMF tones) present in the receive input (Rin) of the echo canceller for a prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo. The NBSD can be disabled by setting the NBDis bit to "1" in Control Register 2. Offset Null Filter Adaptive filters in general do not operate properly when a DC offset is present at any inputs. To remove the DC component, the MT93L00 incorporates Offset Null filters in both Rin and Sin inputs. The offset null filters can be disabled by setting the HPFDis bit to "1" in Control Register 2. ITU-T G.168 Compliance The MT93L00 has been certified G.168 compliant in all 64 ms cancellation modes (i.e., Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester. It should be noted that G.168 compliance is not claimed for the 128 ms Extended Delay mode, although subjectively no difference can be noticed. Device Configuration The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A and B). They can be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figure 6. Normal Configuration In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in Figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously. 26 Zarlink Semiconductor Inc. MT93L04 Back-to-Back Configuration Data Sheet In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 6c. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains undefined data. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo cancellation is required. Back-to-Back configuration is selected by writing "1" into the BBM bit of both Control Register A1 and Control Register B1 of a given group of echo cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured into Back-to-Back. Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a transmission device or between two codecs for echo control on analog trunks. Extended Delay configuration In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller. See Figure 6b. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains undefined data. Extended Delay configuration is selected by writing "1" into the ExtDl bit in Echo Canceller A, Control Register A1. For a given group, only Echo Canceller A, Control Register A1, has the ExtDl bit. Control Register B1, bit-0 must always be set to zero. Table 2 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity. Echo Canceller Functional States Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. Mute In Normal and in Extended Delay configurations, writing a "1" into the MuteR bit replaces Rin with quiet code which is applied to both the Adaptive Filter and Rout. Writing a "1" into the MuteS bit replaces the Sout PCM data with quiet code. 27 Zarlink Semiconductor Inc. MT93L04 Data Sheet Sin echo path A channel A - + Sout Sin echo path A channel A - + Sout Adaptive Filter (64ms) channel A Rin E.C.A channel B Optional -12dB pad Adaptive Filter (128 ms) channel A Optional -12dB pad Rout PORT2 Rout PORT2 Rin PORT1 PORT1 E.C.A b) Extended Delay Configuration (128ms) + Sin echo path + Optional -12dB pad Sout Adaptive Filter (64ms) echo path echo path B channel B Adaptive Filter (64ms) Adaptive Filter (64ms) E.C.B Optional -12dB pad Rout PORT2 E.C.A Optional -12dB pad + E.C.B Rin PORT1 a) Normal Configuration (64ms) c) Back-to-Back Configuration (64ms) Figure 6 - Device Configuration LINEAR 16 bits 2's complement +Zero (quiet code) 0000h SIGN/ MAGNITUDE -Law A-Law 80h CCITT (G.711) -Law FFh A-Law D5h Table 1 - Quiet PCM Code Assignment In Back-to-Back configuration, writing a "1" into the MuteR bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Rout. Writing a "1" into the MuteS bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Sout. In Extended Delay and in Back -to -Back configurations, MuteR and MuteS bits of Echo Canceller B must always be "0". Refer to Figure 4 and to Control Register 2 for bit description. Bypass The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame (125 s) in order to properly clear the filter. Disable Adaptation When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The adaptation process is halted, however, the echo canceller continues to cancel echo. 28 Zarlink Semiconductor Inc. MT93L04 Enable Adaptation Data Sheet In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller to model the echo return path characteristics in order to cancel echo. This is the normal operating state. The echo canceller functions are selected in Control Register A1/B1 and Control Register 2 through four control bits: MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details. MT93L00 Throughput Delay The throughput delay of the MT93L00 varies according to the device configuration. For all device configurations, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and Sin to Sout paths have a delay of two frames. Serial PCM I/O Channels There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output streams is for Rout pcm channels, and the other set is for Sout channels. See Figure 7 for channel allocation. The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set of PCM Send and Receive channels, as illustrated in Figure 4. Serial Data Interface Timing The MT93L00 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz. The input and output data rate of the ST-Bus and GCI bus is 2.048 Mb/s. The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The MT93L00 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way into the bit cell (See Figure 9). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 10). 29 Zarlink Semiconductor Inc. MT93L04 Data Sheet Base Addr + Echo Canceller A 00h Control Reg A1 01h Control Reg 2 02h Status Reg 03h Reserved 04h Flat Delay Reg 05h Reserved 06h Decay Step Size Reg 07h Decay Step Number 08h Control Reg A3 09h Control Reg A4 0Ah Noise Scaling 0Bh Injection Rate 0Ch Rin Peak Detect Reg 0Eh Sin Peak Detect Reg 10h Error Peak Detect Reg 12h Reserved 14h DTDT Reg 16h Reserved 18h NLPTHR 1Ah Step Size, MU 1Ch Reserved 1Eh Reserved Base Addr + Echo Canceller B 20h Control Reg B1 21h Control Reg 2 22h Status Reg 23h Reserved 24h Flat Delay Reg 25h Reserved 26h Decay Step Size Reg 27h Decay Step Number 28h Control Reg B3 29h Control Reg B4 2Ah Noise Scaling 2Bh Injection Rate 2Ch Rin Peak Detect Reg 2Eh Sin Peak Detect Reg 30h Error Peak Detect Reg 32h Reserved 34h DTDT Reg 36h Reserved 38h NLPTHR 3Ah Step Size, MU 3Ch Reserved 3Eh Reserved Figure 7 - Memory Mapping of per channel Control and Status Registers Memory Mapped Control and Status registers Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a "per channel" basis to monitor and control each individual echo canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of Echo Canceller B from group 2. It occupies the internal address space from 0A0h to 0BFh and interfaces to PCM channel #5 on all serial PCM I/O streams. As illustrated in Figure 7, the "per channel" registers provide independent control and status bits for each echo canceller. Figure 8 shows the memory map of the control/status register blocks for all echo cancellers. When Extended Delay or Back-to-Back configuration is selected, Control Register A1/B1 and Control Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section. 30 Zarlink Semiconductor Inc. MT93L04 Data Sheet Table 2 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended Delay or Back-to-Back Normal Configuration For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B, channels 2 and 3 are active. Group 0 1 2 3 4 5 6 7 Channel 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Group 8 9 10 11 12 13 14 15 Channel 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 Table 2 - Group and Channel Allocation Extended Delay Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries don't care data. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B (Channel 5) will carry don't care data. Back-to-Back Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries don't care data. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B (Channel 11) will carry don't care data. 31 Zarlink Semiconductor Inc. MT93L04 Channel 0, EC A Ctrl/Stat Registers Channel 1, EC B Ctrl/Stat Registers 0000h --> 001Fh 0020h --> 003Fh Data Sheet Group 0 Echo Cancellers Registers Group 1 Echo Cancellers Registers Channel 2, EC A Ctrl/Stat Registers Channel 3, EC B Ctrl/Stat Registers 0040h --> 005Fh 0060h --> 007Fh Groups 2 --> 14 Echo Cancellers Registers Group 15 Echo Cancellers Registers Channel 30, EC A Ctrl/Stat Registers Channel 31, EC B Ctrl/Stat Registers 03C0h --> 03DFh 03E0h --> 03FFh Main Control Registers <15:0> Interrupt FIFO Register Test Register 0400h --> 040Fh 0410h 0411h Figure 8 - Memory Mapping Power Up Sequence On power up, the RESET pin must be held low for 100s. Forcing the RESET pin low will put the MT93L00 in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero. When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500s for PLL to lock. C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 16 groups of echo cancellers individually, by writing a "1" into the PWUP bit in each group of echo canceller's Main Control Register. For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute their initialization routine. The initialization routine sets their registers, Base Address+00H to Base Address+3FH, to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00H to Base Address+3FH, for the specific application. Power Management Each group of echo cancellers can be placed in Power Down mode by writing a "0" into the PWUP bit in their respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section for description. 32 Zarlink Semiconductor Inc. MT93L04 The typical power consumption can be calculated with the following equation: PC =9* Nb_of_groups + 3.6, in mW where 0 Data Sheet < Nb_of_groups < 16 Call Initialization To ensure fast initial convergence on a new call, it is important to clear the Adaptive filter. This is done by putting the echo canceller in bypass mode for at least one frame (125 s) and then enabling adaptation. Interrupts The MT93L00 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable is detected and released. Although the MT93L00 may be configured to react automatically to tone disable status on any input PCM voice channels, the user may want for the external HOST processor to respond to Tone Disable information in an appropriate, application specific manner. Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt when a Tone Disable releases. Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory containing the channel number of the echo canceller that has generated the interrupt. All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will toggle low for each pending interrupt. After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 7 for address mapping of Status register). The TD bit indicates the presence of a Tone Disable. The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the MT93L00. To provide more flexibility, the MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked, from generating an interrupt on a per channel basis. Refer to the Registers Description section. JTAG Support The MT93L00 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is controlled by an external Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only. Test Access Port (TAP) The TAP provides access to many test functions of the MT93L00. It consists of three input pins and one output pin. The following pins are found on the TAP. * Test Clock Input (TCK) The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. 33 Zarlink Semiconductor Inc. MT93L04 * Test Mode Select Input (TMS) Data Sheet The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD1 when it is not driven from an external source. * Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VDD1 when it is not driven from an external source * Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high impedance state. * Test Reset (TRST) This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS. Instruction Register In accordance with the IEEE 1149.1 standard, the MT93L00 uses public instructions. The JTAG Interface contains a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. Test Data Registers As specified in IEEE 1149.1, the MT93L00 JTAG Interface contains three test data registers: * Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT93L00 core logic. * * Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO. Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. 34 Zarlink Semiconductor Inc. MT93L04 Register Descriptions Echo Canceller A, Control Register A1 Data Sheet Read/Write Address: 00H + Base Address 0 ExtDl 7 Reset 6 INJDis 5 BBM 4 PAD 3 2 1 0 Bypass AdpDis Reset Value: 00H. Echo Canceller B, Control Register B1 7 Reset Read/Write Address: 20H + Base Address 0 0 6 INJDis 5 BBM 4 PAD 3 2 1 1 Bypass AdpDis Reset Value: 02H. Bit 7 6 5 Name Reset INJDis BBM Description When high, the power-up initialization is executed which presets all register bits including this bit and clears the Adaptive Filter coefficients. When high, the noise injection process is disabled. When low noise injection is enabled. When high the Back to Back configuration is enabled. When low the Normal configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always set both BBM bits of the two echo cancellers (Control Register A1 and Control Register B1) of the same group to the same logic value to avoid conflict. When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low the Rin to Rout path gain is 0 dB. When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on both Sout and Rout is a function of the echo canceller algorithm. When high, echo canceller adaptation is disabled. The MT93L00 cancels echo. When low, the echo canceller dynamically adapts to the echo path characteristics. Bits marked as "1" or "0" are reserved bits and should be written as indicated. When high, Echo Cancellers A and B of the same group are internally cascaded into one 128 ms echo canceller. When low, Echo Cancellers A and B of the same group operate independently. Note: Do not enable both Extended-Delay and BBM configurations at the same time. Control Register B1 bit-0 is a reserved bit and should be written "0". 4 3 PAD Bypass 2 1 0 AdpDis 0 or 1 ExtDl or 0 35 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Control Register A2 Echo Canceller B, Control Register B2 7 TDis Read/Write Address: 01H + Base Address Read/Write Address: 21H + Base Address 0 MuteR 6 5 4 3 2 1 PHDis NLPDis AutoTD NBDis HPFDis MuteS Reset Value: Description 00H. Bit 7 Name TDis When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put into power down mode. When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of the presence/absence of periodic phase reversals. When low, the tone detectors will trigger only upon the presence of a 2100 Hz tone with periodic phase reversals. When high, the non-linear processor is disabled. When low, the non-linear processors function normally. Useful for G.165 conformance testing. When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones. When low, the echo canceller algorithm will remain operational regardless of the state of the 2100 Hz tone detectors. When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled. When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low, the offset nulling filters are active and will remove DC offsets on PCM input signals. When high, data on Sout is muted to quiet code. When low, Sout carries active code. When high, data on Rout is muted to quiet code. When low, Rout carries active code. 6 PHDis 5 NLPDis 4 AutoTD 3 2 NBDis HPFDis 1 0 MuteS MuteR Echo Canceller A, Status Register Echo Canceller B, Status Register 7 res Read Address: Read Address: 1 0 NB 02H + Base Address 22H + Base Address 6 TD 5 DTDet 4 res 3 res 2 res TDG Reset Value: Description 00H. Bit 7 6 Name res TD Reserved bit. Logic high indicates the presence of a 2100 Hz tone. 36 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Status Register Echo Canceller B, Status Register 7 res Read Address: Read Address: 1 0 NB 02H + Base Address 22H + Base Address 6 TD 5 DTDet 4 res 3 res 2 res TDG Reset Value: Description 00H. Bit 5 4 3 2 1 Name DTDet res res res TDG Logic high indicates the presence of a double-talk condition. Reserved bit. Reserved bit. Reserved bit. Tone detection status bit gated with the AutoTD bit. Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100 Hz tone. Logic high indicates the presence of a narrow-band signal on Rin. 0 NB 37 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Flat Delay Register (FD) Echo Canceller B, Flat Delay Register (FD) 7 FD7 6 FD6 5 FD5 4 FD4 3 FD3 2 FD2 1 FD1 0 FD0 Read/Write Address: 04h + Base Address Read/Write Address: 24h + Base Address Power Reset Value 00h Echo Canceller A, Decay Step Number Register (NS) Echo Canceller B, Decay Step Number Register (NS) 7 NS7 6 NS6 5 NS5 4 NS4 3 NS3 2 NS2 1 NS1 0 NS0 Read/Write Address: 07h + Base Address Read/Write Address: 27h + Base Address Power Reset Value 00h Echo Canceller A, Decay Step Size Control Register (SSC) Echo Canceller B, Decay Step Size Control Register (SSC) 7 0 6 0 5 0 4 0 3 0 2 SSC2 1 SSC1 0 SSC0 Read/Write Address: 06h + Base Address Read/Write Address: 26h + Base Address Power Reset Value 04h Note: Bits marked with "0" are reserved bits and should be written "0". Amplitude of MU FIR Filter Length (512 or 1024 taps) 1.0 Step Size (SS) Flat Delay (FD7-0) 2-16 Time Number of Steps (NS7-0) The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one tap is equivalent to 125 s (64 ms/512 taps). 38 Zarlink Semiconductor Inc. MT93L04 Data Sheet FD7-0 Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16). The delay is defined as FD7-0 x 8 taps. For example; if FD7-0 = 5, then MU=2-16 for the first 40 taps of the echo canceller FIR filter. The valid range of FD7-0 is: 0 FD7-0 64 in normal mode and 0 FD7-0 128 in extended-delay mode. The default value of FD7-0 is zero. SSC2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2SSC2-0. For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC2-0 is 04h.NS7-0Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC2-0). The start of the exponential decay is defined as: Filter Length (512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC2-0. For example, if NS7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] = 512 - [4 x (4x24)] = 256 taps for a filter length of 512 taps. Echo Canceller A, Control Register A3 Echo Canceller B, Control Register B3 7 res Read/Write Address: 08H + Base Address Read/Write Address: 28H + Base Address 0 res 6 res 5 res 4 res 3 2 1 RingClr PathClr PathDet Reset Value: Description 0AH. Bit 7-4 3 2 Name res RingClr PathClr Reserved bits. Must always be set to zero for normal operation. When high, the instability detector is activated. When low, the instability detector is disabled When high, the current echo channel estimate will be cleared and the echo canceller will enter fast convergence mode upon detection of a path change. When low, the echo canceller will keep the current path estimate but revert to fast convergence mode upon detection of a path change. Note: this bit is ignored if PathDet is low. When high, the path change detector is activated. When low, the path change detector is disabled. Reserved bit. Must always be set to zero for normal operation. 1 0 PathDet res Echo Canceller A, Control Register A4 Echo Canceller B, Control Register B4 7 0 Read/Write Address: 09H + Base Address Read/Write Address: 29H + Base Address 0 res 6 SD2 5 SD1 4 SD0 3 res 2 res 1 res Reset Value: Description 50H. Bit 7 Name 0 Must be set to zero. 39 Zarlink Semiconductor Inc. MT93L04 Echo Canceller A, Control Register A4 Echo Canceller B, Control Register B4 7 0 Data Sheet Read/Write Address: 09H + Base Address Read/Write Address: 29H + Base Address 0 res 6 SD2 5 SD1 4 SD0 3 res 2 res 1 res Reset Value: Description 50H. Bit 6-4 Name SupDec These three bits control how long the echo canceller remains in a fast convergence state following a path change, Reset or Bypass operation. A value of zero will keep the echo canceller in fast convergence indefinitely. Reserved bits. Must always be set to zero for normal operation. 3-0 res Echo Canceller A, Noise Scaling (NS) Echo Canceller B, Noise Scaling (NS) 7 NS7 6 NS6 5 NS5 4 NS4 3 NS3 2 NS2 1 NS1 Read/Write Address: 0Ah + Base Address Read/Write Address: 2Ah + Base Address 0 NS0 Power Reset Value 74h If the comfort noise level estimator is unable to correctly match the background noise level, this register can be used to scale the comfort noise up or down. A neutral value of 80h will prevent any scaling. Values less than 80h will scale the comfort noise level down. Values greater than 80h will scale the comfort noise level up. Scaling is done linearly, so to scale the comfort noise down by 1 dB, a value of 72h would be used (-1 dB = 89% of original level, 0.89(dec) * 80h = 72h). Similarly, to scale up by 1 dB, use a value of 8Fh (1 dB = 112% of original level, 1.12(dec) * 80h = 8Fh). Echo Canceller A, Injection Rate (IR) Echo Canceller B, Injection Rate (IR) 7 IR7 6 IR6 5 IR5 4 IR4 3 IR3 2 IR2 1 IR1 Read/Write Address: 0Bh + Base Address Read/Write Address: 2Bh + Base Address 0 IR0 Power Reset Value 0Ch The NLP ramps-in comfort noise during the initial background noise estimation stage. This register provides control over the ramp-in speed. Higher values will increase the ramp-in speed. 40 Zarlink Semiconductor Inc. MT93L04 Echo Canceller A, Rin Peak Detect Register 2 (RP) Echo Canceller B, Rin Peak Detect Register 2 (RP) 7 RP15 6 RP14 5 RP13 4 RP12 3 RP11 2 RP10 1 RP9 0 RP8 Data Sheet Read Address: 0Dh + Base Address Read Address: 2Dh + Base Address Power Reset Value N/A Echo Canceller A, Rin Peak Detect Register 1 (RP) Echo Canceller B, Rin Peak Detect Register 1 (RP) 7 RP7 6 RP6 5 RP5 4 RP4 3 RP3 2 RP2 1 RP1 0 RP0 Read Address: 0Ch + Base Address Read Address: 2Ch + Base Address Power Reset Value N/A These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. 41 Zarlink Semiconductor Inc. MT93L04 Echo Canceller A, Sin Peak Detect Register 2 (SP) Echo Canceller B, Sin Peak Detect Register 2 (SP) 7 SP15 6 SP14 5 SP13 4 SP12 3 SP11 2 SP10 1 SP9 0 SP8 Data Sheet Read Address: 0Fh + Base Address Read Address: 2Fh + Base Address Power Reset Value N/A Echo Canceller A, Sin Peak Detect Register 1 (SP) Echo Canceller B, Sin Peak Detect Register 1 (SP) 7 SP7 6 SP6 5 SP5 4 SP4 3 SP3 2 SP2 1 SP1 0 SP0 Read Address: 0Eh + Base Address Read Address: 2Eh + Base Address Power Reset Value N/A These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. Main Control Register 1 Main Control Register 2 Main Control Register 3 Main Control Register 4 Main Control Register 5 Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register 10 Main Control Register 11 Main Control Register 12 Main Control Register 13 Main Control Register 14 Main Control Register 15 (EC group 1) (EC group 2) (EC group 3) (EC group 4) (EC group 5) (EC group 6) (EC group 7) (EC group 8) (EC group 9) (EC group 10) (EC group 11) (EC group 12) (EC group 13) (EC group 14) (EC group 15) Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: 401H 402H 403H 404H 405H 406H 407H 408H 409H 40AH 40BH 40CH 40DH 40EH 40FH 42 Zarlink Semiconductor Inc. MT93L04 Echo Canceller A, Error Peak Detect Register 2 (EP) Echo Canceller B, Error Peak Detect Register 2 (EP) 7 EP15 6 EP14 5 EP13 4 EP12 3 EP11 2 EP10 1 EP9 0 EP8 Data Sheet Read Address: 11h + Base Address Read Address: 31h + Base Address Power Reset Value N/A Echo Canceller A, Error Peak Detect Register 1 (EP) Echo Canceller B, Error Peak Detect Register 1 (EP) 7 EP7 6 EP6 5 EP5 4 EP4 3 EP3 2 EP2 1 EP1 0 EP0 Read Address: 10h + Base Address Read Address: 30h + Base Address Power Reset Value N/A These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: 15h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address: 35h + Base Address 7 DTDT15 6 5 4 3 2 1 0 DTDT8 Power Reset Value 48h DTDT14 DTDT13 DTDT12 DTDT11 DTDT10 DTDT9 (DTDT) Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address: 14h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 1 Read/Write Address: 34h + Base Address 7 DTDT7 6 DTDT6 5 DTDT5 4 DTDT4 3 DTDT3 2 DTDT2 1 DTDT1 0 DTDT0 (DTDT) Power Reset Value 00h This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2's complement linear value defaults to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1. 43 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Non-Linear Processor Threshold Register 2 Read/Write Address: 19h + Base Address Echo Canceller B, Non-Linear Processor Threshold Register 2 Read/Write Address: 39h + Base Address 7 NLP15 6 NLP14 5 NLP13 4 NLP12 3 NLP11 2 NLP10 1 NLP9 0 NLP8 Power Reset Value 0Bh (NLPTHR) Echo Canceller A, Non-Linear Processor Threshold Register 1 Read/Write Address: 18h + Base Address Echo Canceller B, Non-Linear Processor Threshold Register 1 Read/Write Address: 38h + Base Address 7 NLP7 6 NLP6 5 NLP5 4 NLP4 3 NLP3 2 NLP2 1 NLP1 0 NLP0 (NLPTHR) Power Reset Value 60h This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2's complement linear value defaults to 0B60h = 0.0889 or -21.0 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1. Echo Canceller A, Adaptation Step Size (MU) Register 2 Echo Canceller B, Adaptation Step Size (MU) Register 2 7 MU15 6 MU14 5 MU13 4 MU12 3 MU11 2 MU10 1 MU9 0 MU8 Read/Write Address: 1Bh + Base Address Read/Write Address: 3Bh + Base Address Power Reset Value 40h (MU) Read/Write Address: 1Ah + Base Address Read/Write Address: 3Ah + Base Address Echo Canceller A, Adaptation Step Size (MU) Register 1 Echo Canceller B, Adaptation Step Size (MU) Register 1 7 MU7 6 MU6 5 MU5 4 MU4 3 MU3 2 MU2 1 MU1 0 MU0 (MU) Power Reset Value 00h This register allows the user to program the level of MU. MU is a 16 bit 2's complement value which defaults to 4000h = 1.0 The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1. Main Control Register 0 7 WR_all (EC group 0) 2 1 LAW Read/Write Address: 400H 0 PWUP 6 ODE 5 MIRQ 4 MTDBI 3 MTDAI Format Reset Value: Description 00H. Bit 7 Name WR_all Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000h to 0003Fh which is Group 0 address mapping. Useful to initialize the 16 Groups of Echo Cancellers as per Group 0. When low, address mapping is per Figure 8. Note: Only the Main Control Register 0 has the WR_all bit. 44 Zarlink Semiconductor Inc. MT93L04 Main Control Register 0 7 WR_all Data Sheet (EC group 0) 2 1 LAW Read/Write Address: 400H 0 PWUP 6 ODE 5 MIRQ 4 MTDBI 3 MTDAI Format Reset Value: Description 00H. Bit 6 Name ODE Output Data Enable: This control bit is logically AND'd with the ODE input pin. When both ODE bit and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the Main Control Register 0 has the ODE bit. Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The Tone Detectors operate as specified in their Echo Canceller B, Control Register 2. When low, the Tone Detectors Interrupts are active. Note: Only the Main Control Register 0 has the MIRQ bit. Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-magnitude PCM code. A/ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, accept -Law companded PCM code. Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo canceller A and B execute their initialization routine which presets their registers, Base Address+00H to Base Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. 5 MIRQ 4 MTDBI 3 MTDAI 2 Format 1 LAW 0 PWUP 45 Zarlink Semiconductor Inc. MT93L04 Bit 7-5 4 Name unused MTDBI Unused Bits. Description Data Sheet Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM code. A/ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, select m-Law companded PCM code. Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo cancellers A and B execute their initialization routine which presets their registers, Base Address+00H to Base Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. 3 MTDAI 2 Format 1 LAW 0 PWUP Interrupt FIFO Register Read Address: 410H (Read only) 7 IRQ 6 0 5 0 4 I4 3 I3 2 I2 1 I1 0 I0 Reset Value: Description 00H. Bit 7 Name IRQ Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that no interrupt is pending and the FIFO is empty. Unused bits. Always zero 6:5 0 46 Zarlink Semiconductor Inc. MT93L04 Interrupt FIFO Register Read Address: 410H (Read only) Data Sheet 7 IRQ 6 0 5 0 4 I4 3 I3 2 I2 1 I1 0 I0 Reset Value: Description 00H. Bit 4:0 Name I<4:0> I<4:0> binary code indicates the channel number at which a Tone Detector state change has occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated. Test Register Read/Write Address: 411H 7 res 6 res 5 res 4 res 3 res 2 res 1 res 0 Tirq Reset Value: Description 00H. Bit 7:1 0 Name res Tirq Reserved bits. Must always be set to zero for normal operation. Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high, any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its corresponding channel number will be available from the Interrupt FIFO Register. When low, normal operation is selected. Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 I/O Supply Voltage (VDD1) Core Supply Voltage (VDD2) Input on any I/O pins (other than supply pins) Input on any 5 V Tolerant I/O pins Continuous Current at digital outputs Package power dissipation Storage temperature Symbol VDD1 VDD2 VI3 VI5 Io PD TS -55 Min. -0.3 -0.3 VSS - 0.3 VSS - 0.3 Max. 5.0 2.5 VDD1+0.5 5.5 20 2.0 150 Units V V V V mA W C * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. 47 Zarlink Semiconductor Inc. MT93L04 Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 3 4 5 6 Operating Temperature I/O Supply Voltage Core Supply Voltage Input High Voltage on 3.3 V tolerant I/O Input High Voltage on 5 V tolerant I/O Input Low Voltage Sym. TOP VDD1 VDD2 VIH3 VIH5 VIL Min. -40 3.0 1.6 0.7VDD1 0.7VDD1 3.3 1.8 Typ. Max. +85 3.6 1.9 VDD1 5.5 0.3VDD1 Units C V V V V V Data Sheet Test Conditions Device I/O voltage Device core voltage Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 Static Supply Current*** IDD_IO (VDD1=3.3V)*** (single device) IDD_CORE (single device) (VDD2 =1.8V)*** 2 I N P U T S Total Power Consumption for all 4 devices Input High Voltage Input Low Voltage Input Leakage Input Leakage on Pullup Input Leakage on Pulldown I Sym. I CC DD_IO Min. Ty.p Max. 250 Units A mA Test Conditions RESET = 0 32 channels of single device are active 32 channels of single device are active All devices and all 128 channels are active 10 IDD_CORE 65 mA PC 600 mW 3 4 5 VIH VIL IIH/IIL ILU ILD 0.7VDD1 0.3VDD1 -30 30 V V A A A VIN=VSS to VDD1 or 5.5V VIN=VSS VIN=VDD1 See Note 1 IOH = 10 mA IOL = 10 mA VIN=VSS to 5.5V 6 7 8 9 10 O U T P U T S Input Pin Capacitance Output High Voltage Output Low Voltage High Impedance Leakage Output Pin Capacitance CI VOH VOL IOZ CO 3 0.8VDD1 10 0.4 10 pF V V A pF 5 10 Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD1=3.3 V and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN). The *** specifications are for 1 MT93L00 device of the Multi-chip module. 48 Zarlink Semiconductor Inc. MT93L04 Data Sheet AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 3 CMOS Threshold CMOS Rise/Fall Threshold Voltage High CMOS Rise/Fall Threshold Voltage Low Sym. VTT VHM VLM Level 0.5VDD1 0.7VDD1 0.3VDD1 Units V V V Conditions Characteristics are over recommended operating conditions unless otherwise stated AC Electrical Characteristics - Frame Pulse and C4i Characteristic 1 2 3 4 5 6 7 Frame pulse width (ST-BUS, GCI) Frame Pulse Setup time before C4i falling (ST-BUS or GCI) Frame Pulse Hold Time from C4i falling (ST-BUS or GCI) C4i Period C4i Pulse Width High C4i Pulse Width Low C4i Rise/Fall Time Sym. tFPW tFPS tFPH tCP tCH tCL tr, tf i Min. 20 10 10 190 85 85 Typ. Max. 2* tcP-20 Units ns ns ns ns ns ns ns Notes 122 122 244.1 150 150 300 150 150 10 Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD1=3.3V and for design aid only: not guaranteed and not subject to production testing AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic 1 2 3 4 Rin/Sin Set-up Time Rin/Sin Hold Time Rout/Sout Delay - Active to Active Output Data Enable (ODE) Delay Sym. tSIS tSIH tSOD Min. 10 10 Typ. Max. Units ns ns Test Conditions 60 30 ns ns CL=150pF CL=150pF, RL=1K See Note 1 tODE Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing * Note1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 49 Zarlink Semiconductor Inc. MT93L04 Data Sheet tFPW F0i tFPS C4i tSOD Rout/Sout Bit 0, Channel 31 Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT tFPH tCP tCH tCL tr VHM VTT VLM tf VTT tSIS Rin/Sin Bit 0, Channel 31 tSIH Bit 6, Channel 0 Bit 5, Channel 0 Bit 7, Channel 0 VTT Figure 9 - ST-BUS Timing at 2.048 Mb/s tFPW F0i tFPS C4i tSOD Sout/Rout Bit 7, Channel 31) Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 VTT tFPH tCP tCH tCL tr VHM VTT VLM tf VTT tSIS Sin/Rin Bit 7, Channel 31) tSIH Bit 1, Channel 0 Bit 2, Channel 0 Bit 0, Channel 0 VTT Figure 10 - GCI Interface Timing at 2.048 Mb/s ODE tODE Sout/Rout HiZ tODE VTT Valid Data HiZ VTT Figure 11 - Output Driver Enable (ODE) 50 Zarlink Semiconductor Inc. MT93L04 Data Sheet AC Electrical Characteristics - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated. Characteristic 1 Master Clock Frequency, - Fsel = 0 - Fsel = 1 Master Clock Low Master Clock High Sym. fMCF0 fMCF1 tMCL tMCH Min. 19.0 9.5 20 20 Typ. 20.0 10.0 Max. 21.0 10.5 Units MHz MHz ns ns Notes 2 3 Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD1=3.3V and for design aid only: not guaranteed and not subject to production testing tMCH MCLK VTT tMCL Figure 12 - Master Clock 51 Zarlink Semiconductor Inc. MT93L04 AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data delay on read Data hold on read Data setup on write Data hold on write Acknowledgment delay Acknowledgment hold time IRQ delay Sym. tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tDHW tAKD tAKH tIRD 0 20 3 0 0 80 8 65 Min. 0 0 0 0 0 0 79 15 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet Test Conditions CL=150pF, RL=1K CL=150pF, RL=1K See Note 1 CL=150pF, RL=1K CL=150pF, RL=1K, See Note 1 CL=150pF, RL=1K, See Note 1 Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing *Note 1:High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 52 Zarlink Semiconductor Inc. MT93L04 Data Sheet DS tCSS tCSH VTT VTT CS tRWS R/W tADS A0-A10 VALID ADDRESS tRWH VTT tADH VTT tDHR VALID READ DATA tDDR D0-D7 READ D0-D7 WRITE VTT tDSW VALID WRITE DATA tDHW VTT tAKH VTT tIRD tAKD DTA IRQ VTT Figure 13 - Motorola Non-Multiplexed Bus Timing 53 Zarlink Semiconductor Inc. MT93L04 Pin #1 Corner 1 B D F H K M P T V Y 4.00" 45' (4X) 24.00 REF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A C E G J L N R U W 24.00 2 3 4 5 6 7 8 9 14 16 10 12 18 20 15 11 13 17 19 O 1.00 (3X) REF. Data Sheet 0.60 ~ 0.90 (365X) A B C D E F G H J K L M N P R T U V W Y 27.00 0.20 B 24.13 A 30 27.00 0.20 24.13 1.27 1.27 1.17 0.15 (0.56) C Seating Plane 0.50 ~ 0.70 2.33 0.13 MT93L04AG 365 -Ball BGA 54 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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